A (portion of) a 16-bit Dynamic Ram is shown below.
The two reference capacitors are connected to a voltage divider and
so are at VDD/2. The four storage capacitors are disconnected and storing
data. A memory cycle begins by lowering /RAS (Row Address Strobe). Half
of the address (2-bits in this example) is strobed into the ROW ADDRESS
LATCH where it is decoded. The output of the decoder closes the switch
on one of the storage capacitors and throws the switch on the reference
capacitor on the opposite side of the flip-flop (the cross connected FET's).
This drives one side of the flip-flop (the reference side) to ½
VDD and the other side to the voltage currently on the storage capacitor.
Because of the regenerative nature of the flip-flop, if the storage
capacitor voltage is lower than ½ VDD, that side of the flip-flop
goes to zero voltage (the other side to VDD). On the other hand, if the
storage capacitor voltage is greater than ½ VDD, the flip-flop goes
to VDD, driving the other side to ground.
Two things have been accomplished. The flip-flop is set or reset in
accord with the state of the memory capacitor and the memory capacitor
is REFRESHED (driven to 0 or VDD).
/RAS has no further role until sometime in the memory cycle it is raised,
disconnecting the storage capacitor and causing the reference capacitor
to recharge to ½ VDD (This is called the PRECHARGE time).
Next, /CAS is brought low. This latches the other half of the address
into the COLUMN ADDRESS latch where it is decoded. The output of the decoder
closes one of the four switches connecting the READ/WRITE circuitry to
one of the four planes. If the READ/NOT WRITE line is high, it also enables
the three-state output and the output latch. This is then a READ cycle.
When /CAS is raised, the output goes to the Hi-Z state, terminating the
READ. (/RAS, normally, is raised before this).
If READ/WRITE is low when /CAS goes low (or vice-versa), WRITE DATA
is written to the input latch and connected to the READ/WRITE line. This
sets or clears the selected flip-flop and charges or discharges the selected
memory capacitor. This, then is a WRITE cycle.
SRAM MODES
The normal READ and WRITE modes have been described above. There are
other modes.
RAS ONLY REFRESH. We noted that strobing /RAS refreshes a storage capacitor.
Actually, it refreshes one capacitor in each column. If /RAS is returned
high without strobing /CAS, a REFRESH cycle is done. A complete refresh
is accomplished by lower /RAS once for each row address. This must be done
(usually) every 2 mS.
HIDDEN REFRESH. If, while /CAS is held low during a READ cycle, /RAS
is returned high and then strobed again with a different row address, a
hidden refresh is accomplished (i.e. it is done during a READ cycle).
BLOCK READ, BLOCK WRITE. Since a capacitor in each column is sensed
and refreshed with /RAS, holding /RAS low and strobing /CAS with multiple
column addresses allows for BLOCK READS (R/W high) or BLOCK WRITES (R/W
low). This allows reads or writes to be performed faster than individual
reads or writes could be done. The PCI controller for the PENTIUM processor
makes use of this feature.
READ/MODIFY/WRITE. If R/W is high when /CAS is brought low, The data
from the referenced element is latched up in the read latch (and the output
enabled. With both /RAS and /CAS held low, if R/W is brought low, input
data is latched into the input latch and written into the memory capacitor.
This means that you can read data out of a memory location and replace
it with other data all in one (somewhat extended) memory cycle.
DRAM CONTROL
Operation of a DRAM, including refreshing it, is done with a DRAM Controller. This is normally an external controller. There are some quasi-SRAM chips which are really DRAM's with the controller built into the chip so it appears to the outside world as if it were SRAM.