COMBINATIONAL LOGIC REVIEW AND VHDL INTRODUCTION.

• A very quick overview, NOTES15
• The ODD PARITY generator. NOTES08 and NOTES08a
• Formerly an n-input PARITY generator was implemented (or synthesized, to use modern technology) using n-1 exclusive-or gates
• Such circuits could be implemented in PAL type devices using simple HDL's (we used to use ABEL from DataIO).
• Simple PAL type devices may still be used but generally the generator would be incorporated in a CPLD (or FPGA) along with other system components.
• The VHDL description of the ODD PARITY generator
• The "LIBRARY" part of the VHDL file. What libraries to use?
• The "ENTITY" part of the file: The "Black Box description."
• Inputs and outputs are to be specified
• Signals may be "in," "out," "inout," or "buffer." : actually, they could all be called inout and the other terms are primarily for documentation purposes
• Signals may be of various types: Floating point (not very likely), Integers (generally of fixed range), Boolean (False or True, bot often used), Bit (0 or 1), Std_logic (and Std_ulogic) which have values of 0, 1, Z (high impedance), L (low), H (High), U (Unassigned) or X (don't care).
• Note that, other than floating point and integer types, the remaining types are "enumerated" types.
• Buses may be declared by affixing the reserved word, _array to the type and the range (n downto 0, usually).
• The ARCHITECTURAL part of the box - what is it supposed to do?
• Three basic forms of description: Behavioral, Data Flow, and Structural.
• Behavioral descriptions are the most abstract in terms of real hardware but, if written correctly, the most descriptive of what the device is supposed to do.
• Data-Flow descriptions are not often used alone, they may be included in behavioral descriptions.
• Structural descriptions are usually at the higher levels of the design where you "wire together" the black boxes you have described.
• Regardless of which type of description you use, the actual synthesis of the design is likely to be the same. This is especially true in using CPLD's. Unless somehow constrained to do otherwise, the compiler and fitters will synthsize all functions as flat sum-of-product expressions.
• One must have some idea of what the compiler and fitters are doing and a good understanding of the device in order to evaluate the synthesis procedure and deterine that a practical synthesis has been obtained.
• The Adder and VHDL. See NOTES01
 



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