INTRODUCTION TO FINITE STATE MACHINES (FSM)

• THE OUTPUT DECODER
• Supplies output signals based on
• The present state only (Moore Machines)
• The present state and current inputs (Mealy Machines)
• Pure combinational logic - CPE219 material
• THE NEXT STATE DECODER
• Determines the next state based on present state and current inputs
• Pure combinational logic - CPE219 material
• THE MEMORY
• One or more storage elements determine the "state" of the machine
• Storage elements may be unclocked (asynchronous machines)
• SR Latches
• D Latches(?)
• Simple Delay elements
• Storage elements are usually clocked (synchronous machines)
• D Flip-flops (most common today)
• T Flip-flops (common now but were not used in the past)
• JK Flip-flops (previous used quite often, rare today)
• SR (clocked) Flip-flops (found in some gate arrays only)
• Characteristics of (clocked) flip-flops
• Operational Specifications (what do they do?)
• DC specifications (as with gates)
• Timing Specifications
• Setup times
• Hold times
• Clock to output timing
• Clock characteristics
• Minimum clock high
• Minimum clock low
• Minimum clock period (may exceed items (I)+(ii))
• Clock skew
• Specifications when embeded in a PLD (CPLD or FPGA)
• Memory Elements in VHDL. See NOTES02 and NOTES02A
• Intentional Memory Elements (clocked)
• The clk'event status (if clk'event and clk='1')
• Unless somehow specified, assumed to be a D flip-flop
• Unintentional Memory Elements and Asynchronous Ones
• When writing "if (some condition) then x<='1'", what happens when condition is false?
• Must use "if... then... else statements or use "sequential assignment statements."



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