PROGRAMMABLE LOGIC DEVICES (PLD)

• Types of devices
• Programmed Logic Arrays (PLA), the earliest PLD's, not now common
• "PAL"s (a registered tradmark of AMD, now VANTIS), the 22V10 being a very common example and one used in the lab
• CPLD (Complex PLD)'s - Large chips containing from 2 to n(?) PALlike devices with an interconnect matrix to connect them together.
• FPGA (Field Programmable Gate Array) - many small "macrocells" with a very complex signal routing mechanism. These will not be covered in detail.
• Other complex devices (not here covered)
• The PALCE22V10 data sheet and its characteristics
• The fuse array
• The macrocells
• The output cells
• Timing specifications
• The FLASH370i CPLD Family data sheet and its characteristics
• The fuse array
• The macrocells
• The output cells
• The input and clock macrocells
• The product term distribution
• The programmable interconnect matrix
• Timing specifications
• Programming and JTAG
• Other characteristics
• The FPGA
• Refer to information found in VHDL text and refer to ORCA Intro and the full reference manual




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