SYNCHRONOUS SEQUENTIAL LOGIC DESIGN (Sandige, Ch.9)

1. THE DESIGN STEPS
1. Receive specifications from client, supervisor, or whoever it is that wants something designed
2. Review specifications looking for
1. Conflicting specifications
2. Unrealistic specifications
3. Ambiguous specifications
4. Missing specifications
5. Other anomalies in the specifications
3. Reconcile problems found in step ii by
1. Consulting with client, supervisor, or whoever it is that wants the design
2. If (1) not possible, using you own engineering judgment.
4. Draw a block diagram of the entire system
1. If it is a large system, there will be many blocks in the diagram and, in addition, you may need a block diagram detailing one or more blocks in the main diagram
2. Carefully annotate all input and output signals and all signal which interconnect blocks.
3. Be sure to show the type of signal:
1. Standard totem-pole output
2. Three-state buffered output
3. Open Collector and similar outputs
4. Bidirectional signals
5. etc.
5. If the system has more than one block, one or more of the blocks will be a System Controller Block (a FSM)
1. For each system controller, draw a fully annotated State Diagram (or ASM Chart) describing the behavior of the controller. You may wish to use some "schematic capture software for this such as StateCAD.
2. If possible, simulate the operation of the machine at this point (it is possible with StateCAD).
3. Convert (or use software to convert) the state diagram into VHDL code (or whatever HDL is to be used).
4. Select a device (PLD, CPLD for this class) to be used and synthesize the design.
5. Test the design at the compiled level (JEDED fuse file). (Use NOVA in this class).
6. Reiterate steps (1) through (5) if necessary until the desired design is obtained.
7. Program and test Notes #28, Notes #28b, and Notes #28c the device. (also Notes #16) and Notes #16A
2. Designing a simple FSM using StateCAD as a tool (NOTES03 and NOTES03A)
3. State Assignment techniques. (NOTES09)
4. Inputs to FSM's with regard to timing problems (NOTES10) and NOTES 10A
5. Pin Assignments and VHDL (NOTES 11)
6. Binary Encoding vs. One-hot encoding of states (Notes 27)
7. Testing your machine (Notes 28 and Notes 28a and Notes 28b and Notes 28C)
8. Why Mealy Machines are not especially desirable (Notes 30)