ASYNCHRONOUS DESIGN (Sandige, Chapter 10)

1. Replace clocked storage elements with unclocked elements
2. Use of SR latches
3. Use of inherent delay in combinational logic
4. Input rules (primitive machine).
1. Only one input changes at a time - machine reaches steady state before next input change
2. Every input change produces a state change
5. Reducing state diagram or FLOW TABLE (Section 10-3-5 & 6 of Sandige)
6. Making state assignment to eliminate critical races (Section 10-3-7) See NOTES #018
7. From here the design process is very similar to synchronous design. See NOTES #006.
8. An asynchronous Digilock (NOTES #0017) and some problems with it (NOTES #017A)