These notes will be cumulative, added to after each day's lecture. By the end of the quarter, they should contain the entire quarter's notes (more or less). Note that there are hyperlinks in this document which link it to the various NOTES and DATA SHEETS on this site. This will help you to know where in the lectures you will need the notes and data sheets. These notes and those in the links attached are all copyright ©1998 by the Electrical Engineering Department, California Polytechnic State University, San Luis Obispo, CA 93407. All rights reserved.
 

CLASS SYLLABUS

THE LAB

INTRODUCTION TO DIGITAL DESIGN

COMBINATIONAL LOGIC REVIEW

INTRODUCTION TO FINITE STATE MACHINES

PROGRAMMABLE LOGIC DEVICES

SYNCHRONOUS SEQUENTIAL LOGIC DESIGN

ASYNCHRONOUS SEQUENTIAL LOGIC DESIGN

DESIGN PROBLEM - THE RAILROAD GRADE CROSSING
 

• Text Books
• Sandige (should be left over from CPE219)
• VHDL text (contains a $99 version of WARP2)
• Office Hours
• See web site or door outside the office (none on Tuesday)
• Limit of 5 minutes if others waiting
• Best way to ask questions is via e-mail. You should get a response within several hours, weekends included (except in the middle of the night).
• Grading: See syllabus on web site
• Homework
• Use Engineering Paper folded lengthwise with the following on the outside:
• Name
• Course and Section Number
• Date
• Assignment Number
• If you insist, you may work in groups on the homework provided that you turn in one homework paper with the names of each student involved (each student will receive the same score). If you work together and turn in separate papers, you will be docked points (after 35 years of grading papers, I know who works together!). This is not a recommendation to work together, only instructions for those who will do so anyway.
• Be sure your homework papers are complete yet concise. Do not include a lot of meaningless computer printout! Be sure to use standard notation (IEEE Std. 91 for logic diagrams), IEEE standard for VHDL files.
• Homework that is late will not be graded. If you have to turn a paper in late, check with your instructor before the assignment is due.
• Exams
• Exams will be open book, open notes and 50 minutes in duration.
• Students may not work together on exams (Do you want me to split the grade between you?).
• Midterm exams will be returned as quickly as possible after they have been taken. You will have one week from the time you get it back to ask for reconsideration in the grading. After the one week, no changes (other than for clerical errors) will be made.
• The final exam will be two hours in length, open books and notes. It will not be returned to you. You are, however, welcome to come to the office and inspect it.
• Schedule
• Since this is the first quarter the course has been taught using VHDL, the schedule is somewhat tentative. Watch the web site for changes in the schedule.
• There will be a quite of material (notes, data sheets, etc.) on the website which are pertinent to the lecture. This material should be read (and, perhaps, printed) prior to class. I will attempt to indicate which notes and other things are to be read prior to class but it will be, ultimately, your responsibility to see that you have read the correct material.
• The Web sites for this class and for the lab.
• The URL is http://www.ee.calpoly.edu/~wmcmorra/index319.html
• For the lab, http://www.ee.calpoly.edu/~wmcmorra/index359.html
• You will probably want to set book marks in your browsers for these two sites.
• The links on the lecture site are:
• This syllabus
• News of the day (check this frequently)
• Homework assignments (You had better check these!)
• Homework and exam solutions (not the final exam). Note that if you try to access these before they are due, you will get an error message (Access Denied or File Not Found).
• "Notes and things" (see below)
• Your grades. Until the first exam, these will be last years grades. You will be assigned code numbers (1 to 200) and your scores will be posted according to these numbers.
• The "Notes and Things" page
• For many of the items on this site, you will need Adobe Acrobat Reader (the latest version). There is a link on this page to Adobe where you can download it if you do not already have it.
• You will find data sheets (pdf files) for any devices you will need data for.
• You will find links to one or more free software packages. One of these is StateCAD which you should download and install along with the WARP2 from the text.
• You will find a list of links to various sites which deal in one way or another with the subject of VHDL
• You will find these notes along with some detailed notes (pdf) on various subjects. There are also notes on JTAG testing.
• Software Installation - See NOTES14