NOTES & THINGSLast Update on this page 5/14/98 by W.E.McMorran | |
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You will need this to read most of the notes. |
DATA SHEETS |
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| VANTIS | MACH and PAL products from VANTIS (formerly AMD) |
| CYC22V10 | Local Copy of these data sheets. |
| CYPRESS | Download Data Sheets from Cypress Semiconductors |
| FLASH370 | Local copy of the FLASH370 Data Manual |
| PHILIPS | CPLD Data from Philip's Semiconductors |
| XILINX | CPLD Data from Xilinx |
| LATTICE | CPLD Data from Lattice |
| LUCENT | ORCA FPGA Data from Lucent Technology (Bell Labs) |
| INTRO | A local copy of the Introductory ORCA Material |
| FULL | The full 200 page ORCA document |
| OPTOISOLATER | Optoisolator data sheet from Morotola |
| LINE DRIVERS | Line Drivers from T.I. |
| LINE RECEIVERS | Line Receivers from T.I. |
| GATES | Actual crossing gates (and other stuff)from Safetran |
| DACs | Data Sheet for the National DAC08000 DAC |
| ADCs | Data Sheet for the National ADC0800 ADC |
| FAST ADC's | National ADC08060 High Speed ADC |
| NATIONAL | Other National Semiconductor products |
FREE SOFTWARE |
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| StateCAD 3.2 | A local copy of StateCAD 3.2 (Recommended) |
| StateCAD 4.0 | Or, get the latest from Visual Software Solutions |
VHDL SITES |
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| MAIN | The International VHDL Site |
| OTHER | Other sites pertaining to VHDL |
| FILES | Various VHDL Source files (Homework, Notes, Quizes, etc.) |
LECTURE OUTLINE SERIES |
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| BEGIN HERE | This page has the Introduction and also an index. |
| Part 2 | The Lab |
| Part 3 | Introduction to Digital Design |
| Part 4 | Combinational Logic Review |
| Part 5 | Introduction to Finite State Machines |
| Part 6 | Introduction to Programmable Logic Devices |
| Part 7 | Synchronous Sequential Logic Design |
| Part 8 | Asynchronous FSM Design |
| Part 9 | The Dreaded Rail Road Grade Crossing |
| Part 10 | THE BEGINNING OF THE ELEVATOR PROBLEM |
| Part 11 | The Buttons and Lamps |
| Part 12 | The floor Controller |
| Part 13 | Where's the elevator? |
| Part 14 | Reed Switches |
| Part 15 | The main Controller |
| Part 16 | THE WATTMETER PROBLEM |
| Part 17 | Sources of Errors |
| Part 18 | Sample Multiplications |
| Part 19 | Booths' Multiplication Algorithm |
| Part 20 | Interface with the ADC |
| Part 21 | NOTES ON JTAG AND ISP |
| Part 22 | JTAG - Part 2 |
| Part 23 | JTAG - Part 3 |
| Part 24 | JTAG - Part 4 |
| Part 25 | JTAG - Part 5 |
| Part 26 | JTAG - Using JTAG to program FLASH370 devices with ISP |
MISCELLANEOUS NOTESNote: The above lecture series has links to most of these notes. Note also that these notes are not arranged in any particular order. |
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| Notes #000 | The ADDER and VHDL - an introduction. |
| Notes #001 | The ADDER and VHDL - another introduction. |
| Notes #002 | The Flip-flop and Macro Cell |
| Notes #002a | An addendum to Notes #002 |
| Notes #003 | An Introduction to state machines |
| Notes #003a | An addendum to notes #003 - Analysis |
| Notes #004 | An FSM design example - The Dreaded Railroad Crossing! |
| Notes #004a | An animated description of - The Dreaded Railroad Crossing! |
| Notes #004b | Real Crossing Gate Equipment! |
| Notes #005 | The Railroad Crossing problem revisited. |
| Notes #005b | The design done entirely with StateCAD |
| Notes #005a | The Crossing Gate. |
| Notes #006 | The Mechanics of Asynchronous Design. |
| Notes #007 | The Economics of Design. |
| Notes #008 | VHDL and the Flat Design Problem. |
| Notes #008a | A continuation of Notes #008 |
| Notes #009 | StateCAD and State Assignment Considerations. |
| Notes #010 | The "too short," the "mistimed," and the "too long" input pulses. |
| Notes #010a | Debouncing switches and buttons. |
| Notes #011 | VHDL and making specific pin assignments. |
| Notes #012 | Interpretation of JEDEC Files. |
| Notes #013 | Building a Clock Generator for the Lab. |
| Notes #014 | StateCAD and WARP2 Installation notes. |
| Notes #015 | A Quick Overview of WARP2 and VHDL. |
| Notes #016 | Doing Simulation in StateCAD. |
| Notes #016a | An Animated demonstration of the above. |
| Notes #017 | An Asynchronous FSM Design Example, The DIGILOCKASYNC |
| Notes #017a | Why the above machine may fail and what to do about it! |
| Notes #018 | State Assignments in Asynchronous Machines |
| Notes #019 | Your legal and ethical responsibility as a Computer or Electrical Engineer. |
| Notes #020 | Creating and using a LOOKUP table in VHDL. |
| Notes #021 | Dynamic RAM Description and Operation. |
| Notes #022 | Material related to Midterm Two (CPE319-02, Winter 1998). |
| Notes #023 | VHDL and READ-ONLY MEMORY |
| Notes #024 | ADDER Design Considerations in VHDL |
| Notes #025 | What's all that in the WARP Report? |
| Notes #026 | Life Without StateCAD |
| Notes #027 | Binary vs. One-Hot assignments : Normal vs Buffered outputs< |
| Notes #028 | Testing your FSM |
| Notes #028a | Alternate notes on testing your FSM |
| Notes #028b | Automated Testing of FSM's |
| Notes #028c | More Accurate Test Procedures. |
| Notes #029 | Why You Don't Want to Design Mealy Machines |
| Notes #030 | A Comparison of controllers using CPLD's and MicroControllers |
