------------------------------------------------------------------------
-- CPE 269 VHDL File: bin_sseg_dec.vhd
-- Experiment 2: drives 7-segment displays with binary values. This
--               circuit expects a fast clock in order to properly 
--               multiplex the displays. 
--
-- Author: bryan mealy  (06-01-04)
--
--  
-- revisions: 
------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------------------------------------------------
-- interface specification
--------------------------------------------------------------
entity bin_sseg_dec is
    Port (       Y : in std_logic_vector(3 downto 0);
               CLK : in std_logic;
           disp_en : out std_logic_vector(3 downto 0);
          segments : out std_logic_vector(7 downto 0));
end bin_sseg_dec;


--------------------------------------------------------------
-- display driver circuit description 
--------------------------------------------------------------
architecture my_ckt of bin_sseg_dec is

   signal cnt_dig : std_logic_vector(1 downto 0); 
   signal   digit : std_logic; 

begin
   process (clk)
   begin
      if (rising_edge(CLK)) then 
            cnt_dig <= cnt_dig + 1; 
      end if; 
   end process; 

   -- sends "1" or "0" to display ---------------------------
   segments <= "11000000" when digit = '0'  else
            "11111001" when digit = '1'  else
            "11111111"; 

   -- multiplexes the displays -----------------------------
   disp_en <= "1110" when cnt_dig = "00" else 
              "1101" when cnt_dig = "01" else
              "1011" when cnt_dig = "10" else
              "0111" when cnt_dig = "11" else
              "1111"; 

   -- send the data to the correct display -----------------
   digit <= Y(3) when cnt_dig = "00" else 
            Y(2) when cnt_dig = "01" else
            Y(1) when cnt_dig = "10" else
            Y(0) when cnt_dig = "11" else
            '0'; 

   end my_ckt;