------------------------------------------------------------------------
-- CPE 269 VHDL File: univ_sr.vhd
-- Experiment 3: Behavioral implemenation of a  Universal Shift Register
--
-- Author: bryan mealy  (06-06-04)
--
-- revisions: 
------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-----------------------------------------------------------------
-- Interface for universal shift register 
-----------------------------------------------------------------
entity univ_sr is
    Port (    SEL : in std_logic_vector(1 downto 0);
           D_LOAD : in std_logic_vector(7 downto 0);
            D_OUT : out std_logic_vector(7 downto 0);
              CLK : in std_logic;
      DR_IN,DL_IN : in std_logic);
end univ_sr;

-----------------------------------------------------------------
-- functional description of universal shift register 
-----------------------------------------------------------------
architecture my_sr of univ_sr is
   -- intermediate signal declaration 
   signal tmp_d : std_logic_vector(7 downto 0); 
begin
   -- assign final output values
   D_OUT <= tmp_d; 

   process (CLK) 
   begin
      if (rising_edge(CLK)) then  
         case SEL is 
            -- do nothing (don't change state) --------------
            when "00" =>  tmp_d <= tmp_d;   

            -- parallel load --------------------------------
            when "01" =>  tmp_d <= D_LOAD; 
            
            -- shift right ----------------------------------
            when "10" =>  tmp_d <= DL_IN & tmp_d(7 downto 1);
            
            -- shift left ----------------------------------- 
            when "11" =>  tmp_d <= tmp_d(6 downto 0) & DR_IN;
            
            -- default case --------------------------------- 
            when others => tmp_d <= "00000000"; 
         end case;  
      end if; 
   end process; 

end my_sr;