ELECTRICAL ENGINEERING DEPARTMENT
California Polytechnic State University
EE 307: DIGITAL ELECTRONICS AND INTEGRATED CIRCUITS Winter Quarter 2021 

Catalog Description 
Analysis, design, application and interfacing of integrated logic circuits, including NMOS, CMOS, TTL, ECL, and other logic families. Prerequisites: CPE 129/169 and EE 306/346. Concurrent: EE 347, CPE 229 or CPE 233 (may be taken previously).  
Instructor/Office/ 
David Braun [dbraun@calpoly.edu] 
20304 
7561464 

Office Hours 
Monday,
Wednesday 11:10Noon, 

Textbook 
PLEASE READ AHEAD OF LECTUREIntroduction to Digital Microelectronic Circuits by K. Gopalan, Irwin, 1996 or newer. Errata Packet of Supplemental Material Available from Cal Poly Bookstore 

References 



Lecture with classroom instruction, problems and examples. READ the textbook. Weekly homework assignments are due before the BEGINNING of class on the days indicated.* After working problems INDIVIDUALLY, I encourage you to consult with colleagues to compare approaches and results. Solutions posted on web on due date. Check your final exam schedule now. Exams are closed book. If you must miss an exam, make arrangements with me at least 3 weeks in advance. You may use a note sheet during midterm and final exams. 

Grading 


