CMOS Inverters:
A simple description of the characteristics of CMOS inverters by Bruce Sales
CMOS inverters (Complementary NOSFET Inverters) are some of the most widely used and adaptable MOSFET inverters used in chip design. They operate with very little power loss and at relatively high speed. Furthermore, the CMOS inverter has good logic buffer characteristics, in that, its noise margins in both low and high states are large.
This short description of CMOS inverters gives a basic understanding of the how a CMOS inverter works. It will cover input/output characteristics, MOSFET states at different input voltages, and power losses due to electrical current.
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal, were VIN is connected to the gate terminals and VOUT is connected to the drain terminals.(See diagram). It is important to notice that the CMOS does not contain any resistors, which makes it more power efficient that a regular resistorMOSFET inverter.As the voltage at the input of the CMOS device varies between 0 and 5 volts, the state of the NMOS and PMOS varies accordingly. If we model each transistor as a simple switch activated by VIN, the inverter’s operations can be seen very easily:
Transistor "switch model"
The switch model of the MOSFET transistor is defined as follows:
MOSFET 
Condition on MOSFET 
State of MOSFET 
NMOS 
Vgs<Vtn 
OFF 
NMOS 
Vgs>Vtn 
ON 
PMOS 
Vsg<Vtp 
OFF 
PMOS 
Vsg>Vtp 
ON 
When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging VOUT to logic high. When Vin is high, the NMOS is "on and the PMOS is "on: draining the voltage at VOUT to logic low.
This model of the CMOS inverter helps to describe the inverter conceptually, but does not accurately describe the voltage transfer characteristics to any extent. A more full description employs more calculations and more device states.
Multiple state transistor model
The multiple state transistor model is a very accurate way to model the CMOS inverter. It reduces the states of the MOSFET into three modes of operation: CutOff, Linear, and Saturated: each of which have a different dependence on Vgs and Vds. The formulas which govern the state and the current in that given state is given by the following tabel:
NMOS Characteristics 

Condition on V_{GS} 
Condition on V_{DS} 
Mode of Operation 

I_{D} = 0 
V_{GS} < V_{TN} 
All 
Cutoff 
I_{D} = k_{N} [2(V_{GS}  V_{TN} ) V_{DS}  V_{DS}^{2} ] 
V_{GS} > V_{TN} 
V_{DS} < V_{GS} V_{TN} 
Linear 
I_{D} = k_{N} (V_{GS}  V_{TN} )^{2} 
V_{GS} > V_{TN} 
V_{DS }> V_{GS} V_{TN} 
Saturated 
PMOS Characteristics 

Condition on V_{SG} 
Condition on V_{SD} 
Mode of Operation 

I_{D} = 0 
V_{SG} < V_{TP} 
All 
Cutoff 
I_{D} = k_{P} [2(V_{SG} + V_{TP} ) V_{SD}  V_{SD}^{2} ] 
V_{SG} > V_{TP} 
V_{SD} < V_{SG} +V_{TP} 
Linear 
I_{D} = k_{P} (V_{SG} + V_{TP} )^{2} 
V_{SG }> V_{TP} 
V_{SD} > V_{SG} +V_{TP} 
Saturated 
In order to simplify calculations, I have made use of an internet circuit simulation device called "MoHAT." This tool allows the user to simulate circuits containing a few transistors in a simple and visually appealing way. The circuits shown below show the state of each transistor (black for cutoff, red for linear, and green for saturation) accompanied by the voltage transfer characteristic curve (VOUT vs. VIN). The vertical line plotted on the VTC corresponds to the value of VIN on the circuit diagram. The following series of diagrams depict the CMOS inverter in varying input voltages ranging from low to high in ascending order.
Table of figures 

figure 
mode of operation 
Logic output level 
1 
VIN < VIL 
High 
2 
VIN < VIL 
High 
3 
VIL < VIN <VIH 
<undetermined> 
4 
VIN > VIH 
Low 
5 
VIN > VIH 
Low 
Power dissapation analysis of CMOS inverter
As I mentioned before, the CMOS inverter shows very low power dissipation when in proper operation. In fact, the power dissipation is virtually zero when operating close to VOH and VOL. The following graph shows the drain to source current (effectively the overall current of the inverter) of the NMOS as a function of input voltage. Note that the current in the far left and right regions (low and high VIN respectively) have low current, and the peak current in the middle is only .232mA (a 1.16mW power dissipation).
Conclusion
The CMOS inverter is an important circuit device that provides quick transition time, high buffer margins, and low power dissipation: all three of these are desired qualities in inverters for most circuit design. It is quite clear why this inverter has become as popular as it is.