EE 307 - Digital Integrated Electronics

 


Last Updated January 6, 2019

Comments about text by Gopalan

Other typographical errors appear in the EE 307 supplemental material packet

Page Where Comment
10 Fig. 1.4 For an inverter, VOH is the output voltage when the input voltage is VOL, not VIL.
Please define VOH(MIN) as the output voltage when the input voltage is VIL.

Similarly, VOL is the output voltage when the input voltage is VOH, not VIH.
Please define VOL(MAX) as the output voltage when the input voltage is VIH.

See revised figure.

For a non-inverting buffer, adjust subscripts appropriately to obtain VOH(MIN) as the output voltage when the input voltage is VIH.
12 Eqn. 1.5 5 - 2(Vi - 1)2, for Vi between 1 and 2.35 V
16 Fig. 1.8

The low to high propagation delay, tPLH, measures the time elapsed between the 50% point on the input waveform and the 50% point on the output waveform.

See revised figure.

16 last full change form to from
61 last full The equation should read I = (10 V - 0.6 V)/1.01 kOhm.
66-67 PSpice

The PSpice input decks require a white space between Element Name, Node 1, and Node 2
For example, R115 1K should be R1 1 5 1K to show R1 between nodes 1 and 5.
The example on p. 69 shows the correct syntax.

134 Fig. P3.7c Label 1 k ohm resistor between the +15V supply and the BJT collector RC.
144 1st Eqn. VC = VO = VBE(SAT) + (VCC - VBE(SAT))*(RB/N)/(RC + (RB/N))
179 Table 4.2 With 1.2 V < VIN < 1.5V, Q1 operates in Saturation.
189 15th line The collector is then clamped at 0.4 V BELOW the base, so the transistor can't saturate.
192 Fig. 4.29c X-axis label should indicate VO vs. VI NOT VO vs. VO
222 last vt = 2.6 mv should be vt = 26 mV
228 last line 120 should be 120 mV
240 9th line -IERC1 = -0.93 V should be -IERC1 = -0.87 V
240 Equation after
9th line
1.63 V should be -1.57 V
279 4th line =0.7 V should be = -0.7 V
305 Fig. 6.10 RD = 1 kOhm
308 3rd "With gate and body connected together . . . ." should be "With gate and drain connected together . . . ."
308 3rd "Hence, the plot of sqrt(ID) = VGS in saturation . . . ." should be "Hence, the plot of sqrt(ID) vs. VGS in saturation . . . ."
308 4th "At VSG = 4V, substrate . . . ." should be "At VGS = 4V, substrate . . . ."
309 Fig. 6.16 RD = 2 kOhm
310 14th line "using Equations (6.18) and (6.19)" should be "using Equations (6.12) and (6.19)" In fact, he should use Equations (6.12) and (6.20).
339 Fig 7.1c Pinch-off should be Ohmic
341 After Eqn. 7.5a dVo/dVi = 2Vo/ [2Vo + 1 - 2Vi]
346 Eqn. 7.22 Replace KR by (KR)1/2
347 Fig. 7.5a VDSD should be VGSD
381 After Eqn. 7.67 (See Figure 7.17e)
398 Eqn. 7.83 50[2(4 - VM)(5 - VX) - (5 - VX)2] = 50 (VX - VM - 1)2
398 Last line VSG = VDD should be VG = 0 V
400 Eqn. 2 & 3 RHS has subscript "P" which should be "N"
406 Fig. 7.34a MN2 is a NMOS, so the arrow should point from body (ground) to channel.
408 End of 2nd Paragraph Delete the last sentence, because power dissipation takes place when M2 turns on, with the clock either high or low.
416 Last line PMOSFET MP operates in the linear region.
464 Eq. 8.1 IB1 has the units of mA.
466 3rd line Q3 should be QS instead
473 2nd full "saturation emitter current of Q1" should be "saturation emitter current of Q2"
497 Fig. 8.38 Note that the output amplifier A is an inverting amplifier
500 Eqn. 8.30 T = Ton + Toff = (RA + 2RB)C ln 2
562 Last sentence R/_W should be _R/W

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