| EE 307 |
TRANSLATION BUFFER DESIGN PROJECT
|
Braun
|
Hello professor Braun, we are in the middle of our design project and are having trouble picking W/L ratio's. Could you PLEASE give us some direction of picking the ratios. So far we have been guessing, making W larger than L. Thanks a lot To pick W/L ratios, estimate the maximum or average current that you require the FET to provide to meet timing and logic level requirements. Use transconductance and threshold voltage data from the PSpice models as a guide and calculate the required W/L ratios. This could save you much time. One of the questions I asked during group formation regarded the supply voltage Vdd (for the CMOS inverter). I don't recall whether or not we had free reign to modify that value. Could you please verify whether or not we can modify Vdd? Thanks for the help. You may select power rail values for your buffer portion of the circuit. Vcc and Vdd equal 5 V. Note the voltage requirements at nodes 11 and Vout. Additional references: Analysis and Design of Digital Integrated Circuits by D.A. Hodges and H.G. Jackson, 2nd edition, McGraw Hill, 1988, p. 408-411 Microelectronic Circuit Design by R. C. Jaeger, McGraw Hill, 1997, pp. 375-377 Digital Integrated Circuits: A Design Perspective by J.M. Rabaey, Prentice Hall, 1995, p. 446-454 http://www.ee.calpoly.edu/~dbraun/courses/ee307/W02/Project.html contains PSpice data. [ Braun's Home Page | EE307 | EE347 | E-mail | Schedule | Courses | Research | Polymer Electronics | Sr. Projects ] |