EE 347 - Guidelines for Lab Reports

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Pre-lab									10-20 points
Data, Results, and Post-lab Analysis					15-30 points
Technical and Learning Content, Completeness, Commentary [TLCCC]       7.5-10.0 points
Presentation, Professionalism, Legibility [PPL]			       2.5-5 points

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Total									35-60 points

Please record relevant data, sketch results accurately, note numerical values, and generally document that you performed all tasks requested in the Lab Manual. Did the results agree with expectations? Did you encounter any problems? Quantity does not necessarily equal quality, so be concise. With a copy of the Lab Manual and your report, I should see exactly what you did, how you did it, what results you obtained, and read careful and clear explanations of all KEY issues. Please apply the Paramedic Method and use the active voice! Read my comments on use of active and passive voice. If you want your instructor to ignore something you write, use the passive voice. More on experiments 1, 2, 3, 4, 5, 6, 7, 8, & 9.

Here are a few additional requirements:

• Answer all how and why questions.
• Each PSpice simulation should show input decks (.cir files), clearly-annotated output plots, and a circuit diagram with node names labeled. Include your name in the first comment line of the .cir file.
• Annotate all plots clearly. Label signals, data, axes, units, and don't assume that your audience can read your mind. Axis labels belong outside the plot area, usually along the left side and across the bottom.
• For oscilloscope traces, align signal grounds with scope gridlines on screen.
• Each plot and table requires a caption and number. Refer to each plot and table in your narrative. Full page plots can make a report more tedious to read, so combine smaller plot(s) and narrative on the same page when feasible.
• Number the pages of your report. Orient text and figures and staple pages to enable the reader to view them from the bottom or right hand side of the page.
• Report data using appropriate units, the appropriate number of significant figures and error bars.
• Compare results with predicted and simulated values.
• Provide adequate and COMPLETE bibliographic references, for example, cite urls of web pages for data sheets and cite other information you obtain from books, including your textbook. List author and title. Cite references in your narrative within square brackets. If necessary in a worst case, indicate author unknown. Use the IEEE Style:
  [1] H. Bronleigh, “IEEE Style,” Home - IEEE Style - LibGuides at Murdoch University, January 2020. [Online]. Available: https://libguides.murdoch.edu.au/IEEE/all. [Accessed: Feb. 10, 2020]
  [2] Institute of Electrical and Electronics Engineers, Inc., IEEE Transactions, Journals and Letters: Information for Authors. Piscataway NJ: IEEE, 2006. Available: http://www.ieee.org/portal/cms_docs/pubs/transactions/auinfo03.pdf. [Accessed February 23, 2007] pp. 4-5 .
• Document any troubleshooting completely.

Negative Points	-3	-2	-1	-0
Evidence, Reasoning & Critical Thinking	Poor evidence, reasoning or critical thinking.	More evidence, reasoning, or critical thinking missing.	A lack of evidence, reasoning, or critical thinking.	Each topic sentence supported by evidence, reasoning, and critical thinking.
Clarity, Grammar & Spelling	More than four grammar and/or spelling errors	Three or four grammar and/or spelling errors	One or two errors in grammar/spelling	All grammar and spelling are correct
Followed guidelines in How to Prepare EE 347 Lab Reports	Four or more errors or missing two of the sections required by Table III	Three or four errors or missing one of the sections required by Table III	One or two errors	Yes
References	No references	Too few references or more than two citation errors.	Enough references, some cited incorrectly	Enough references, cited completely & correctly. Has authors

General Tips

• Use grounded wrist-straps when handling MOS chips.
• Use scope probes when measuring circuit waveforms using the oscilloscope.
     Confirm scope probe ratio, prior to capturing scope data.
     Align signal grounds with scope gridlines on screen.
     Avoid pressing the "autoscale" button, unless you want your instructor to leave.
• Annotate and label all plot axes and data curves, including scope captures.

Below, please find more specific tips for

Experiment 1
Experiment 2
Experiment 3
Experiment 4
Experiment 5
Experiment 6
Experiment 7
Experiment 8
Experiment 9

Experiment 1 Tips

Experiment 1 has a long pre-lab, so start it early. Re-read How to Prepare EE 347 Lab Reports.

• Each PSpice simulation should show input decks (.cir files), clearly-annotated output plots, and a circuit diagram with node names labeled. Include your name in the first comment line of the .cir file.
• Annotate and label all plot axes and data curves.
     For example, list V_GS values on multiple Output Characteristic curves and list V_DS values on multiple Output Characteristic curves.
     You may write these labels by hand. Type any other work not turned in prior to the end of the lab session.
• Show your work for all calculations. Use and indicate correct units such as Volts, Amps, and Watts.
• Calculation 1
     Determine V_TN and k_N from the Output Characteristics.
     Determine V_TN and k_N from the Transfer Characteristics.
  Explain why values obtained from the Output and Transfer Characteristics do not necessarily equal each other.
  By completing experiment 1, you should obtain NMOS FET PSpice parameters to use in subsequent simulations. Careful work can lead to parameters that provide more accurate simulation results than those on page 2-4.
  When extracting device parameters from data:
     1. Select data point(s) thoughtfully to include useful data;
     2. Clearly identify which data point(s) you used; and
     3. Do use a linear least square fit to extract the slope of measured data.
• Complete Calculations 1 - 4 during the lab session.
• This experiment requires an antistatic wrist strap, so use the one from your EE 346 labkit, if you don't have a nicer one.

Experiment 2 Tips

Experiment 2 pre-lab simulations sometimes prove challenging, so start early enough to ask your instructor questions.

• Each PSpice simulation should show input decks (.cir files), clearly-annotated output plots, and a circuit diagram with node names labeled. Include your name in the first comment line of the .cir file.
• Please prevent artificial kinks in DC simulation results due to specifying a too large voltage step in the .DC statement:
           .DC    start    stop    step
  I recommend you specify a step voltage no greater than 20 mV for stop - start = 5 V. For example:   
           .DC    Vin   0.0    5.0    0.02
• Annotate and label all plot axes and data curves.
     For example, label R_L values on simulated and measured VTCs for circuit 2.2a.
     For example, label critical voltages on simulated and measured VTCs for all circuits.
     You may write these labels by hand. Type any other work not turned in prior to the end of the lab session.
• Note and record measured (not only nominal) values for all components, including V_DD, V_GG, and R_L.
• Use the appropriate number of significant figures and error bars. For example, V_OL ≠ 0 V.
• From pre-lab simulations and measured data, extract and record critical voltages according to Figure 2.3.
• Consult http://courseware.ee.calpoly.edu/courseware/ee347/EE347_EXPT2.doc. Include in your report Appendix I.
     Fill in the simulation table before class, to use in your pre-lab quiz.
     Fill in the measured data table during class.
     Compare measured data to simulated data and explain both agreement and disagreement.
• Sustainability Analysis
     Explain how experiment topics or applications related to the experiment foster or prevent sustainability.
     Consider issues related to Energy, Environment, Economics, and social or political Equity, four “E”s of sustainability. Include Commoner's Laws of Ecology.
     Use the wiki and references posted on Canvas™.

Experiment 3 Tips

• Each PSpice simulation should show input decks (.cir files), clearly-annotated output plots, and a circuit diagram with node names labeled. Include your name in the first comment line of the .cir file.
• Please prevent artificial kinks in transient simulation results due to not specifying the maximum time step PSpice uses in the calculations. To specify a smaller step_ceiling, use the .TRAN statement:
            . TRAN    print_step    final_time    (results_delay)    (step_ceiling)
  The last two parameters are officially optional, but I recommend that you
  specify a step_ceiling no greater than the smaller of final_time/1000 or (rise or fall time)/10. For example:   
           .TRAN    1 ns    200 ns     0     200 ps
• Annotate and label all plot axes and data curves.
     For example, label t_PLH and t_PHL values on simulated and measured data.
     For example, label V_IN and t_OUT curves on simulated and measured plots.
     You may write these labels by hand. Type any other work not turned in prior to the end of the lab session.
• Use the appropriate number of significant figures and error bars.
     For example, t_PLH ≠ 0, t_PHL ≠ 0, t_R ≠ 0, and t_F ≠ 0.
• Note and record measured (not only nominal) values for all components, including V_DD, C_L, and frequency.
• Consult http://courseware.ee.calpoly.edu/courseware/ee347/EE347_EXPT3.doc. Include as your report cover page according to the Abbreviated Report Format for Experiments 3 and 7.
     Fill in the simulation table before class, to use in your pre-lab quiz.
     Fill in the measured data table during class.
     Compare measured data to simulated data and explain both agreement and disagreement. Specifically,
        Explain how and why the three circuits have different speeds.
        Explain how and why the load capacitance, C_L, influences speed.

Experiment 4 Tips

• Consult http://courseware.ee.calpoly.edu/courseware/ee347/EE347_EXPT4.doc. Include in your report Appendix I.
     Fill in the simulation table before class, to use in your pre-lab quiz. Since the simulation requires more than the 10
     transistor limit for the PSpice student edition, so use the Professional version available in several on-campus computer
     labs and EE labs.
     Fill in the measured data table during class.
     Compare measured data to simulated data.
• Circuits 1 & 2 use V_DD = 8 V.
     Determine whether circuits 1 & 2 signals swing rail-to-rail.
     Explain why or why not.
• Circuits 3 - 6 use V_DD = 5 V.
     Measure and explain any RC time constants observed on output signals, both qualitatively and quantitatively.
     Provide or calculate magnitudes for R and C components.
     Specify physical origins for both R and C components.
• Exercise great care, if using a FET connected to the CD 4007 chip pins 7 or 14 (Q₃ or Q₆ in App. A, Fig. 1.1).
• Sustainability Analysis
     Explain how experiment topics or applications related to the experiment foster or prevent sustainability.
     Consider issues related to Energy, Environment, Economics, and social or political Equity, four“E”s of sustainability. Include Commoner's Laws of Ecology.
     Use the wiki and references posted on Canvas™.
     

Experiment 5 Tips

• http://courseware.ee.calpoly.edu/courseware/ee347/ contains no online data sheet for Experiment 5.
• In the pre-lab simulation, use two input voltage pulse statements to create the clock and anti-clock signals.
  Do NOT drive V_IN with a pulse statement. Drive V_IN with feedback inverter. If you use the PSpice professional version and want to make the simulation more challenging, then use the TTL inverter found in Fig. 6-1 with a 1 kohm pull-up resistor at its output. If you use the PSpice student version with a 10 transistor limit, then use a CMOS inverter as the feedback inverter.
• Note from the lab manual Appendix A how the 7400 (TTL), 74LS00 (Low-power Schottky TTL), 74C00, and 74HC00 (CMOS) chips all use the same pinout. The CD4007, 4001B, and CD4016 CMOS chips have different pinouts. Use CMOS inside the shift register.
• Prepare a 1 kHz timing diagram with all traces plotted on the same page and time scale, preferably on different plot axes to facilitate comparison. Support with clearly labeled scope captures.
• Maximum operation frequency
     Include one scope capture at the highest frequency with correct operation, and
     Include another scope capture at the next highest frequency to illustrate the failure mode.
• Minimum operation frequency
     Include one scope capture at the lowest frequency with correct operation, and
     Include another scope capture at the next lowest frequency to illustrate the failure mode.
• Sustainability Analysis
     Explain how experiment topics or applications related to the experiment foster or prevent sustainability.
     Consider issues related to Energy, Environment, Economics, and social or political Equity, four“E”s of sustainability. Include Commoner's Laws of Ecology.
     Use the wiki and references posted on Canvas™.

Experiment 6 Tips

• Consult http://courseware.ee.calpoly.edu/courseware/ee347/EE347_EXPT6.doc. Include in your report Appendix I.
• Don't underestimate the pre-lab.
     Calculate the average gate power by averaging power over an integral number of periods, not fractional periods.
     Gate Power = P_GATE = Σ (V * I) = V_DD * I_DD + V_IN * I_IN - V_OUT * I_OUT
     If your simulated gate only "dissipates" negative power, check your signs.
     Positive PSpice currents flow into components.
• Note from the lab manual Appendix A how the 7400 (TTL), 74LS00 (Low-power Schottky TTL), 74C00, and 74HC00 (CMOS) chips all use the same pinout. The 4007 and 4001 CMOS chips have different pinouts.
• Section 2 & 3 power dissipation data
     Present in tabular form as shown on p. 6-5.
     Carefully produce a log-log plot as shown on p. 6-6.
• Fill in and explain p. 6-7
  
  

Experiment 7 Tips

• Consult http://courseware.ee.calpoly.edu/courseware/ee347/EE347_EXPT7.doc. Include as your report cover page according to the Abbreviated Report Format for Experiments 3 and 7.
  
• The pre-lab requires you to select resistor values.
     After calculating desired resistor values, select real 5% tolerance resistors.
     Real resistors may require further calculations or a trip to the nearest resistor store.
• Annotate OR and NOR VTC plots.
     Label V_R values and critical voltages.
     Label critical voltages.
• Explain both the negative and positive slope sections in the NOR VTC plot for V_IN above V_IH.
  Why doesn't the OR VTC have these features?
• Note criteria used to distinguish maximum load tolerated. Explain calculations.
• Save this circuit to use in Experiment 9 as the 5V PECL gate. While experiment 9 indicates a need to redesign the gate, the only required design involves the reference voltage generation circuit. Experiment 9 can use the same resistor values as Experiment 7.
  

Experiment 8 Tips

• Consult http://courseware.ee.calpoly.edu/courseware/ee347/EE347_EXPT8.doc. Include in your report Appendix I.
  
• Read the hint for the pre-lab simulation on p. 8-2. Also, take care that transitions on D do not coincide with transitions of the clock.
• Use TTL or LS-TTL for all gates, EXCEPT the inverters in part 3, the ET-D-FF.
• A glitch means a brief high voltage on a low logic signal or a brief low voltage on a high logic level. To simulate an endless supply of glitches during the experiment, apply a square wave to the D input. Determine whether the D flip-flop or the edge-triggered D flip-flop are transparent (let's glitches through) or opaque (blocks glitches).
• A latch or flip-flop may toggle (i.e. oscillate), when the Not Q output feeds back into the D input. To test for toggling, wire D = Not Q.
  

Experiment 9 Tips

• Consult http://courseware.ee.calpoly.edu/courseware/ee347/EE347_EXPT9.doc. Include in your report Appendix I.
  
• Include circuit diagram(s) for the reference voltage generation circuit you design and supporting calculations.
• Include circuit diagram(s) for the interface circuits you design and supporting calculations. Don't just pick any circuit out of Gopalan, because it looks promising. You may find it easier to design your own.
• While experiment 9 indicates a need to redesign the -5.2 V ECL gate to work as +5 V PECL, the only required design involves the reference voltage generation circuit. Experiment 9 can use the same resistor values as Experiment 7, if your Experiment 7 ECL gate worked. We can live with the 0.2 V rail-ro-rail change.
• For current spike measurements, indicate measured voltage, current, and R_S values.