Brian Hood

George Elder-Groebe

Tsz Kin Lau

Design Project

 

Design Process:

We first started with a three-stage amplifier. We based this circuit on figure 15.1 in the book. We found that there were too many capacitors for our liking. Our second design was an active load differential amplifier to a common emitter BJT. With this design we got an unwanted output at low frequencies. We then switched to a common-drain MOSFET as our output stage. This enabled us to remove both the emitter resistor and the collector resistor left over from the BJT stage. We also removed the coupling capacitors, which greatly reduced the total area and lowered our FOM. We decided to use a Widlar current source for the differential amplifier. Our first current source didn’t supply enough current for the differential stage, so the output was clipped at the positive rail. We modified the current source to supply more current to the differential amplifier. We tried a few different resistor values for the current source until the output stopped clipping. We ended up with a current supply of 1.08 mA.

Our final circuit was an active load differential amplifier with a Widlar current source, and common-drain MOSFET output stage.

FOM = (Power)*(Area)/(Gain @ 50kHz)

= (44.7mW) * (206um2) / (820.6)

= 11.22

Final Schematic:

 

 

 

Ic, Ids

Vce, Vds

gm

rP

ro

Q1

536uA

9.99V

21.44mS

4.66kW

205.2kW

Q2

540uA

5.747V

21.6mS

4.63kW

195.8kW

Q3

520uA

0.6492V

20.8mS

4.81kW

193.6kW

Q4

542uA

4.892V

21.68mS

4.61kW

193.5kW

Q5

1.079mA

5.0325V

43.16mS

2.32kW

97.3kW

M1

1.64mA

8.1911V

1.29mS

¥

4.99kW

 

Differential Stage:

RIN = rP 1 + rP 2 || (R3 + ro5)

= 9.088kW

ROUT = ro2 || ro4

= 97.3kW

AV1 = gm2*ro4/2

= 2090

Output Stage:

RIN = ¥

ROUT = 1/ gm6

= 775.2W

AV2 = gm*RL/(1+ gm*RL)

= 0.56

Total Gain:

AV = AV1 * AV2

= 1176

PSpice Input Deck:

*Design Project

*Differential to Common Collector Amplifier

VCC 1 0 DC 10.0V

VEE 12 0 DC -10.0V

VS 5 0 SIN (0 2m 50K)

RS 4 5 1K

Q1 2 4 6 CA3096N

Q2 3 0 6 CA3096N

Q3 2 2 1 CA3096P

Q4 3 2 1 CA3096P

Q5 6 7 8 CA3096N

M1 1 3 11 11 CMOSN L=1U W=6U

R1 7 12 10K

R2 7 0 10K

R3 8 12 4K

RL 11 0 1K

.MODEL CA3096N NPN (IS=10.000E-15 BF=466.52 VAF=100 IKF=14.030E-3

+ ISE=74.093E-15 NE=1.6606 BR=.1001 VAR=100 IKR=10.010E-3

+ ISC=10.000E-15 NK=.46898 RC=10 CJE=1.2825E-12 MJE=.33333

+ CJC=786.59E-15 MJC=.33333 TF=490.39E-12 XTF=5.3212 VTF=28.396

+ ITF=.27408 TR=10.000E-9)

.MODEL CA3096P PNP (IS=10.000E-15 BF=94.511 VAF=100 IKF=1.1177E-3

+ ISE=976.47E-15 NE=1.9980 BR=.1001 VAR=100 IKR=10.010E-3

+ ISC=10.000E-15 NK=.53243 CJE=1.4535E-12 MJE=.33333 CJC=3.8474E-12

+ MJC=.33333 TF=24.300E-9 XTF=10.054 VTF=9.7920 ITF=1.2571

+ TR=10.000E-9)

.MODEL CMOSN NMOS LEVEL=3 PHI=0.600000 TOX=1.7800E-08 XJ=0.200000U TPG=1

+ VTO=0.7623 DELTA=7.6940E-01 LD=1.1890E-07 KP=1.2379E-04

+ UO=638.1 THETA=1.2160E-01 RSH=6.5980E+00 GAMMA=0.5942

+ NSUB=4.0030E+16 NFS=7.0730E+12 VMAX=1.9160E+05 ETA=4.3410E-02

+ KAPPA=1.0510E-01 CGDO=3.4599E-10 CGSO=3.4599E-10

+ CGBO=4.1520E-10 CJ=2.6473E-04 MJ=0.9561 CJSW=4.0556E-10

+ MJSW=0.270227 PB=0.800000

.MODEL CMOSP PMOS LEVEL=3 PHI=0.600000 TOX=1.7800E-08 XJ=0.200000U TPG=-1

+ VTO=-0.8814 DELTA=1.2220E+00 LD=4.5410E-08 KP=3.6685E-05

+ UO=189.1 THETA=1.7250E-01 RSH=5.5000E-01 GAMMA=0.4652

+ NSUB=2.4540E+16 NFS=7.7440E+12 VMAX=3.7770E+05 ETA=8.1730E-02

+ KAPPA=9.9830E+00 CGDO=1.3214E-10 CGSO=1.3214E-10

+ CGBO=4.2612E-10 CJ=5.5813E-04 MJ=0.4968 CJSW=2.0919E-10

+ MJSW=0.463227 PB=0.850000

.TRAN .1U 60u 0 .1U

.PROBE

.END

 

Bodeplot:

 

1kHz Plot:

 

50kHz Plot: