The CMOS Inverter Explained

Basil Shelley

bshelley@calpoly.edu

EE-307; Dr. Braun; F02

 

 

Overview

Complementary MOSFET (CMOS) technology is widely used today to form circuits in numerous and varied applications.  Today’s computers CPUs and cell phones make use of CMOS due to several key advantages.  CMOS offers low power dissipation, relatively high speed, high noise margins in both states, and will operate over a wide range of source and input voltages (provided the source voltage is fixed).  Next I will attempt to explain just how this logic gate works now that you have some idea of how important CMOS is in your day-to-day life.

 

 

 

CMOS Inverter Basics

As you can see from Figure 1, a CMOS circuit is composed of two MOSFETs.  The top FET (MP) is a PMOS type device while the bottom FET (MN) is an NMOS type.  The body effect is not present in either device since the body of each device is directly connected to the device’s source.  Both gates are connected to the input line.  The output line connects to the drains of both FETs. 

 

Take a look at the VTC in Figure 2.  The curve represents the output voltage taken from node 3.  You can easily see that the CMOS circuit functions as an inverter by noting that when VIN is five volts, VOUT is zero, and vice versa. Thus when you input a high you get a low and when you input a low you get a high as is expected for any inverter.  You might be wondering what happens in the middle, transition area of the curve.  You might also be curious as to what modes of operation the MOSFETs are in.  We will look at these issues next.

 

 

                      

                          Figure 1:  CMOS Inverter                                                                      

      

                

              Figure 2:  Basic Voltage Transfer Characteristic

 

 

 

DC Analysis

Figure 3 shows a more detailed VTC.  Before we begin our analysis it is important to mention three items.

 

 

Figure 3:  VTC with Input Signal

 

Region I

 

First we focus our attention on region I.  In this case when we apply an input voltage between 0 and VTN.  The PMOS device on since a low voltage is being applied to it.  The NMOS is already negative enough and has no use for more free electrons so it refuses to conduct and turns into a large resistor.  Since the NMOS device is on vacation, there is no current flow through either device.  VDD is available at the Vo terminal since no current is going through the PMOS device and thus no voltage is being dropped across it.

 

 

Region II

 

Here we raise the input voltage above VTN.  We find that the PMOS device remains in the linear region since it still has adequate forward bias.  The NMOS turns on and jumps immediately into saturation since it still has a relatively large VDS across it.

 

 

The maximum allowable input voltage at the low logic state (VIL) occurs in this region.  VIL is the value of Vi at the point where the slope of the VTC is -1.  Put another way, VIL occurs at (dVo/dVi)=-1. 

 

Region III

 

In the middle of this region there exists a point where Vi=Vo.  We label this point VM and identify it as the gate threshold voltage.  The voltage dropped across the NMOS device equals the voltage dropped across the PMOS device when the input voltage is VM.  For a very short time, both devices see enough forward bias voltage to drive them to saturation. 

 

 

Region IV

 

Region IV occurs between an input voltage slightly higher than VM but lower than VDD-VTP.  Now the NMOS device is conducting in the linear region, dropping a low voltage across VDS.  Since VDS is relatively low, the PMOS device must pick up the tab and drop the rest of the voltage (VDD-VDS) across its VSD junction.  This, in turn, drives the PMOS into saturation.  This region is effectively the reverse of region II.

 

 

The minimum allowable input voltage at the logic high state (VIH) occurs in this region.  VIH occurs at the point where the slope of the VTC is –1 (dVo/dVi)=-1.

 

Region V

 

The NMOS wants to conduct but its drain current is severely limited due to the PMOS device only letting through a tiny leakage current.  The PMOS is out to lunch since it is seeing a positive drive but it is already positive enough and has no use for more.  This drain current let through by the PMOS is too small to matter in most practical cases so we let ID=0.  With this information we can conclude that VDS=Vo=0 V for the NMOS since no current is going through the device.  We have, in effect, sent in VDD and found the inverter’s output to be zero volts.  For CMOS inverters, VOH=VDD.  VOL is defined to be the output voltage of the inverter at an input voltage of VOH.  We have just proven that VOL=0.

 

 

 

 

A Few Words About Power Dissipation

Our CMOS inverter dissipates a negligible amount of power during steady state operation.  Power dissipation only occurs during switching and is very low.  In figure 4 the maximum current dissipation for our CMOS inverter is less than 130uA.  Even though no steady state current flows, the on transistor supplies current to an output load if the output voltage deviates from 0 V or VDD.  This makes CMOS technology useable in low power and high-density applications.

 

 

Figure 4 – Drain Current Verses Input Voltage

 

 

PSPICE Code

If you have a lot of free time on your hands try pasting this code into PSPICE.  Try changing some of the transistor parameters such as W, L, and KP.

 

* CMOS INVERTER

VDD 1 0 5

VIN 2 0

MQ1 1 2 3 1 PMOD1

MQ2 3 2 0 0 NMOD1

.DC VIN 0. 5. .01

 

* NMOS MODEL DEFINITION

.MODEL NMOD1 NMOS (L=3U W=6U KP=69U GAMMA=0.37

+LAMBDA=0.06 RD=1 RS=1 VTO=1.0 TOX=0.04U

+CBD=2F CBS=2F CJ=200U CGBO=200P CGSO=40P CGDO=40P)

 

* PMOS MODEL DEFINITION

.MODEL PMOD1 PMOS (L=3U W=6U KP=34.5U GAMMA=-0.37

+LAMBDA=0.06 RD=1 RS=1 VTO=-1.0 TOX=0.04U

+CBD=2F CBS=2F CJ=200U CGBO=200P CGSO=40P CGDO=40P)

 

.PRINT DC V(1) V(2) V(3)

.PROBE

.END

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